Need help with testbench driving serial data out @ different clock rates, Please :)

Ok, my comments on the existing code.

1. Why is the clock period 2 ps? the default modelsim resultion is 100ps and anything less than this will probably round to nearest? this models a 500 GHz clock (i know it doesnt really matter, because it's event driven). But wouldnt it be better to have some more-realistic or easier to read clock (like 10 ns)?

2. The data should be generated in the main process, not in a separate process. You should just generate words as you need them and then loop through the word to send it over the sdi. Generating the data as you need it will give you more freedom to input data at different speeds. You can have as many sets of seeds as you want to control the different input frames.

3. With VHDL 2008 you have hierarchical signal referencing, so you can access the internal clocks from your testbench. The easiest way would be to alias the internal signal and then use it locally:

alias internal_192khz : std_logic is <<signal tdm_uut.some_ent1.some_ent2.clk_192khz : std_logic >>;

This way you can ensure the data is properly aligned with the clock.