Need help on a design constraint file for a IP

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Check if the clock names between quotes match those feeding the relevant TSE mac pins in your Quartus design.

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Yes I think they do match. Here is the instantiation of the TSE mac IP and attached is the complete sdc file for the TSE core.

I have generated four ports in my IP, and the sdc file has a mechanism converting the names for all the four ports.

Instantiation of my IP in the quartus design:

triple_mac triple_mac_inst(

.clk(sys_clk),

.reset(~rst_n),

.address(reg_address),

.read(reg_read),

.writedata(reg_writedata),

.write(reg_write),

.rx_afull_clk(),

.rx_afull_channel(),

.rx_afull_data(),

.rx_afull_valid(1'b0),

.data_tx_data_0(data_tx_data_0),

.data_tx_eop_0(data_tx_eop_0),

.data_tx_error_0(data_tx_error_0),

.data_tx_sop_0(data_tx_sop_0),

.data_tx_valid_0(data_tx_valid_0),

.data_rx_ready_0(data_rx_ready_0),

.tx_clk_0(tx_clk_0),

.rx_clk_0(rx_clk_0),

.gm_rx_d_0(gm_rx_d_0),

.gm_rx_dv_0(gm_rx_dv_0),

.gm_rx_err_0(gm_rx_err_0),

.m_rx_d_0(m_rx_d_0),

.m_rx_en_0(m_rx_en_0),

.m_rx_err_0(m_rx_err_0),

.m_rx_col_0(m_rx_col_0),

.m_rx_crs_0(m_rx_crs_0),

.set_10_0(set_10_0),

.set_1000_0(set_1000_0),

.tx_crc_fwd_0(tx_crc_fwd_0),

.data_tx_data_1(data_tx_data_1),

.data_tx_eop_1(data_tx_eop_1),

.data_tx_error_1(data_tx_error_1),

.data_tx_sop_1(data_tx_sop_1),

.data_tx_valid_1(data_tx_valid_1),

.data_rx_ready_1(data_rx_ready_1),

.tx_clk_1(tx_clk_1),

.rx_clk_1(rx_clk_1),

.gm_rx_d_1(gm_rx_d_1),

.gm_rx_dv_1(gm_rx_dv_1),

.gm_rx_err_1(gm_rx_err_1),

.m_rx_d_1(m_rx_d_1),

.m_rx_en_1(m_rx_en_1),

.m_rx_err_1(m_rx_err_1),

.m_rx_col_1(m_rx_col_1),

.m_rx_crs_1(m_rx_crs_1),

.set_10_1(set_10_1),

.set_1000_1(set_1000_1),

.tx_crc_fwd_1(tx_crc_fwd_1),

.data_tx_data_2(data_tx_data_2),

.data_tx_eop_2(data_tx_eop_2),

.data_tx_error_2(data_tx_error_2),

.data_tx_sop_2(data_tx_sop_2),

.data_tx_valid_2(data_tx_valid_2),

.data_rx_ready_2(data_rx_ready_2),

.tx_clk_2(tx_clk_2),

.rx_clk_2(rx_clk_2),

.gm_rx_d_2(gm_rx_d_2),

.gm_rx_dv_2(gm_rx_dv_2),

.gm_rx_err_2(gm_rx_err_2),

.m_rx_d_2(m_rx_d_2),

.m_rx_en_2(m_rx_en_2),

.m_rx_err_2(m_rx_err_2),

.m_rx_col_2(m_rx_col_2),

.m_rx_crs_2(m_rx_crs_2),

.set_10_2(set_10_2),

.set_1000_2(set_1000_2),

.tx_crc_fwd_2(tx_crc_fwd_2),

.readdata(reg_readdata),

.waitrequest(waitrequest),

.mac_tx_clk_0(mac_tx_clk_0),

.mac_rx_clk_0(mac_rx_clk_0),

.data_tx_ready_0(data_tx_ready_0),

.data_rx_data_0(data_rx_data_0),

.data_rx_valid_0(data_rx_valid_0),

.data_rx_eop_0(data_rx_eop_0),

.data_rx_sop_0(data_rx_sop_0),

.data_rx_error_0(data_rx_error_0),

.pkt_class_data_0(pkt_class_data_0),

.pkt_class_valid_0(pkt_class_valid_0),

.gm_tx_d_0(gm_tx_d_0),

.gm_tx_en_0(gm_tx_en_0),

.gm_tx_err_0(gm_tx_err_0),

.m_tx_d_0(m_tx_d_0),

.m_tx_en_0(m_tx_en_0),

.m_tx_err_0(m_tx_err_0),

.ena_10_0(),

.eth_mode_0(eth_mode_0),

.mac_tx_clk_1(mac_tx_clk_1),

.mac_rx_clk_1(mac_rx_clk_1),

.data_tx_ready_1(data_tx_ready_1),

.data_rx_data_1(data_rx_data_1),

.data_rx_valid_1(data_rx_valid_1),

.data_rx_eop_1(data_rx_eop_1),

.data_rx_sop_1(data_rx_sop_1),

.data_rx_error_1(data_rx_error_1),

.pkt_class_data_1(pkt_class_data_1),

.pkt_class_valid_1(pkt_class_valid_1),

.gm_tx_d_1(gm_tx_d_1),

.gm_tx_en_1(gm_tx_en_1),

.gm_tx_err_1(gm_tx_err_1),

.m_tx_d_1(m_tx_d_1),

.m_tx_en_1(m_tx_en_1),

.m_tx_err_1(m_tx_err_1),

.ena_10_1(),

.eth_mode_1(eth_mode_1),

.mac_tx_clk_2(mac_tx_clk_2),

.mac_rx_clk_2(mac_rx_clk_2),

.data_tx_ready_2(data_tx_ready_2),

.data_rx_data_2(data_rx_data_2),

.data_rx_valid_2(data_rx_valid_2),

.data_rx_eop_2(data_rx_eop_2),

.data_rx_sop_2(data_rx_sop_2),

.data_rx_error_2(data_rx_error_2),

.pkt_class_data_2(pkt_class_data_2),

.pkt_class_valid_2(pkt_class_valid_2),

.gm_tx_d_2(gm_tx_d_2),

.gm_tx_en_2(gm_tx_en_2),

.gm_tx_err_2(gm_tx_err_2),

.m_tx_d_2(m_tx_d_2),

.m_tx_en_2(m_tx_en_2),

.m_tx_err_2(m_tx_err_2),

.ena_10_2(),

.eth_mode_2(eth_mode_2));

And I got warnings from compilation like:Ignored filter at triple_mac_constraints.sdc: clk could not be matched with a port

Ignored filter at triple_mac_constraints.sdc:mac_tx_clk_0 could not be matched with a port.

Ignored create_clock at triple_mac_constraints.sdc: Argument <> is an empty collection

...

...

Almost all of the constraints were ignored due to naming problems.

By the way, I didn't run any tcl before using the IP.

Quartus generated a triple_mac_constraints.tcl and a

triple_mac_nativelink.tcl with the IP.

Do I need to run some scripts before starts using a IP core?

I'm not an expert on this point, but I think there are mismatches between the top level signals and the names in the contraints file

For example

set CLK "clk" , but you clock is called sysclk in the top level

set TX_CLK "tx_clk" , but this is tx_clk_0/_1/_2 at the top level

and so on.

The Megafunction Wizard generated a .v file for the IP. If I used the .v file of the IP as a top module and compile, it would work but if I instantiate the IP in my design module, all of the constraints were ignored.

I'm wondering that might be because the hierarchy path in the generated sdc file is not set correctly. But I have tried all of the combinations like top.triple_mac_inst, etc.

Does anyone have an idea about this...

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I'm not an expert on this point, but I think there are mismatches between the top level signals and the names in the contraints file

For example

set CLK "clk" , but you clock is called sysclk in the top level

set TX_CLK "tx_clk" , but this is tx_clk_0/_1/_2 at the top level

and so on.

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But if I used the IP module as the top module, it would work.

The IP module still use the name of tx_clk_0/_1/_2,etc.