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Altera_Forum
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14 years ago

Need help on a design constraint file for a IP

Hi there, I am using Altera's Triple_Speed_Ethernet Mac IP core. And while I was compiling the IP with my design, there prompts warnings that lots of constraints in the generated sdc file from...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

The Megafunction Wizard generated a .v file for the IP. If I used the .v file of the IP as a top module and compile, it would work but if I instantiate the IP in my design module, all of the constraints were ignored.

I'm wondering that might be because the hierarchy path in the generated sdc file is not set correctly. But I have tried all of the combinations like top.triple_mac_inst, etc.

Does anyone have an idea about this...