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Altera_Forum
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14 years ago

Need help on a design constraint file for a IP

Hi there, I am using Altera's Triple_Speed_Ethernet Mac IP core. And while I was compiling the IP with my design, there prompts warnings that lots of constraints in the generated sdc file from...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

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I'm not an expert on this point, but I think there are mismatches between the top level signals and the names in the contraints file

For example

set CLK "clk" , but you clock is called sysclk in the top level

set TX_CLK "tx_clk" , but this is tx_clk_0/_1/_2 at the top level

and so on.

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But if I used the IP module as the top module, it would work.

The IP module still use the name of tx_clk_0/_1/_2,etc.