Need help for constraining 12-bit serial ADC

I'm using an ADC12DS080, a 80MHz 12-bit serial ADC. It has 2 channels per an input so that every edge of the frame clock I get a new sample. I use the data_clk as the DDR input clock and I believe I have that constrained correctly according to the guides. However, I can't seem to get the frame_clk's relationship with the data_clk correct. It keeps coming out as .001. when it should be around 1.042 ns. The data_clk is 240 MHz and the frame_clk is 40MHz. I shift the frame_clk by 2.081 ns to get the frame_clk in sync with delay from the DDIO_INPUT megafunction. I then also generate a 80MHz clock with the same delay.

create_clock -name fpga_clk_frame -period 25 # # VIRTUAL CLOCK DATA# #
create_clock -name ext_clk1 -period 4.167# # INPUT CLOCK WITH 90 DEGREES PHASE SHIFT
create_clock -name fpga_clk_data -period 4.167 -waveform {1.042 3.125} # ##################3 FAST ADC# ####################################3
set_input_delay -clock ext_clk1 -max 0.250 }]
set_input_delay -clock ext_clk1 -min -0.250 }]
set_input_delay -clock ext_clk1 -max 0.250 }] -clock_fall -add_delay
set_input_delay -clock ext_clk1 -min -0.250 }] -clock_fall -add_delay
set_input_delay -clock ext_clk1 -max 0.250 }]
set_input_delay -clock ext_clk1 -min -0.250 }]
set_input_delay -clock ext_clk1 -max 0.250 }] -clock_fall -add_delay
set_input_delay -clock ext_clk1 -min -0.250 }] -clock_fall -add_delay
set_false_path -setup -rise_from  -fall_to 
set_false_path -setup -fall_from  -rise_to 
set_false_path -hold -rise_from  -rise_to 
set_false_path -hold -fall_from  -fall_to 
set_false_path -setup -rise_from  -rise_to 
set_false_path -hold -rise_from  -rise_to