Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Need help for constraining 12-bit serial ADC

I'm using an ADC12DS080, a 80MHz 12-bit serial ADC. It has 2 channels per an input so that every edge of the frame clock I get a new sample. I use the data_clk as the DDR input clock and I believe I ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

I would of never though of that. Thanks for the help. Timequest now gives a proper relationship of 1.041ns.