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Altera_Forum
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14 years ago

Need help for constraining 12-bit serial ADC

I'm using an ADC12DS080, a 80MHz 12-bit serial ADC. It has 2 channels per an input so that every edge of the frame clock I get a new sample. I use the data_clk as the DDR input clock and I believe I ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

The 4.167 won't line up with 25ns, it lines up with 25.002ns. So they're not considered to be related. Make the other clocks 4.166 and FRCLK 24.996. (I figure it's better to make them tighter instead of leaving the other clock at 4.167 and loosening the FRCLK to 25.002ns.