Need advice about coding style

A slightly quirky one, I agree. However, the following code is confusing Quartus:

  IF ci = '0' THEN
   co <= aab;
  ELSIF ci = '1' THEN
   aob := axb XOR aab; -- the same as (a OR b)
   co <= aob;
  END IF;

  IF ci = '0' THEN
   co <= aab;
  ELSE
   aob := axb XOR aab; -- the same as (a OR b)
   co <= aob;
  END IF;

thanks for advice.

An another comment on coding style - the conv_std_logic_vector and conv_integer functions come from the non-standard std_logic_unsigned and std_logic_arith packages. You shouldnt use them, as they are non-standard. You should use the numeric_std package instead. (and probably use appropriate types to avoid type conversion as much as possible - you can use non-std_logic_vector types in ports - like unsigned or signed type.).

thanks for advice

Ok. I know how to use UNSIGNED ports. I make an example:

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY full_adder_Nbit IS
GENERIC (
	N : POSITIVE := 4
);
PORT (
	ci : IN  STD_LOGIC := '0';
	a  : IN  UNSIGNED (N-1 DOWNTO 0) := X"0";
	b  : IN  UNSIGNED (N-1 DOWNTO 0) := X"0";
	s  : OUT UNSIGNED (N-1 DOWNTO 0) := X"0";
	co : OUT STD_LOGIC := '0'
);
END full_adder_Nbit;
ARCHITECTURE b OF full_adder_Nbit IS
BEGIN
	p0 : PROCESS(ci, a, b)
	VARIABLE
		result_v : UNSIGNED (0 TO N+1);
	BEGIN
		result_v := ('0' & a & '1') + ('0' & b & ci);
		co <= result_v(0);
		s  <= result_v(1 TO N);
	END PROCESS p0;
END b;

For your questions.

I've changed as you wish. But I am confused what's wrong with my previous. I agree that no extra bit requried in variable , but the reverse order - i'm confused. I can only suggest that LSB is always at index 0 but I am not sure about it. If your advice is coming from code can be read clearly, i accept it.

ARCHITECTURE b OF full_adder_Nbit IS
BEGIN
	p0 : PROCESS(ci, a, b)
	VARIABLE
		result_v : UNSIGNED (N DOWNTO 0);
	BEGIN
		result_v := ('0' & a ) + ('0' & b) + ('0' & ci);
		co <= result_v(N);
		s  <= result_v(N-1 DOWNTO 0);
	END PROCESS p0;
END b;

Ok. Another one example. If I make my adder synchronus. Will be my code suitable for real application?

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY full_adder_Nbit IS
GENERIC (
	N : POSITIVE := 4
);
PORT (
	clk : IN STD_LOGIC := '0';
	ci : IN  STD_LOGIC := '0';
	a  : IN  UNSIGNED (N-1 DOWNTO 0) := X"0";
	b  : IN  UNSIGNED (N-1 DOWNTO 0) := X"0";
	s  : OUT UNSIGNED (N-1 DOWNTO 0) := X"0";
	co : OUT STD_LOGIC := '0'
);
END full_adder_Nbit;
ARCHITECTURE b OF full_adder_Nbit IS
	SIGNAL
		reg_a,
		reg_b,
		out_s : UNSIGNED (N-1 DOWNTO 0);
	SIGNAL
		reg_ci,
		out_co : STD_LOGIC;
BEGIN
	p0 : PROCESS (clk)
	BEGIN
		IF rising_edge(clk) THEN
			reg_a <= a;
			reg_b <= b;
			reg_ci <= ci;
		END IF;
	END PROCESS p0;
	p1 : PROCESS(reg_ci, reg_a, reg_b)
	VARIABLE
		result_v : UNSIGNED (N DOWNTO 0);
	BEGIN
		result_v := ('0' & reg_a) + ('0' & reg_b) + ('0' & reg_ci);
		out_co <= result_v(N);
		out_s  <= result_v(N-1 DOWNTO 0);
	END PROCESS p1;
	p2 : PROCESS (clk)
	BEGIN
		IF falling_edge(clk) THEN
			co <= out_co;
			s  <= out_s;
		END IF;
	ENd PROCESS p2;
END b;

in principle the addition (combinatorial only) will do the job.

thank you, Kaz.