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Altera_Forum's avatar
Altera_Forum
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11 years ago

Need advice about coding style

Hello I'm Alex and I am novice for VHDL coding. if my english awful pls forgive me. I trying to understand VHDL PROCESS statement. I try with 1bit full adder with carry save function in Quartus2 v...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

I've changed as you wish. But I am confused what's wrong with my previous. I agree that no extra bit requried in variable , but the reverse order - i'm confused. I can only suggest that LSB is always at index 0 but I am not sure about it. If your advice is coming from code can be read clearly, i accept it. 

ARCHITECTURE b OF full_adder_Nbit IS
BEGIN
	p0 : PROCESS(ci, a, b)
	VARIABLE
		result_v : UNSIGNED (N DOWNTO 0);
	BEGIN
		result_v := ('0' & a ) + ('0' & b) + ('0' & ci);
		co <= result_v(N);
		s  <= result_v(N-1 DOWNTO 0);
	END PROCESS p0;
END b;