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Altera_Forum
Honored Contributor
11 years agoNeed advice about coding style
Hello I'm Alex and I am novice for VHDL coding. if my english awful pls forgive me. I trying to understand VHDL PROCESS statement. I try with 1bit full adder with carry save function in Quartus2 v...
Altera_Forum
Honored Contributor
11 years agoAn another comment on coding style - the conv_std_logic_vector and conv_integer functions come from the non-standard std_logic_unsigned and std_logic_arith packages. You shouldnt use them, as they are non-standard. You should use the numeric_std package instead. (and probably use appropriate types to avoid type conversion as much as possible - you can use non-std_logic_vector types in ports - like unsigned or signed type.).