Ok. I know how to use UNSIGNED ports. I make an example:
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY full_adder_Nbit IS
GENERIC (
N : POSITIVE := 4
);
PORT (
ci : IN STD_LOGIC := '0';
a : IN UNSIGNED (N-1 DOWNTO 0) := X"0";
b : IN UNSIGNED (N-1 DOWNTO 0) := X"0";
s : OUT UNSIGNED (N-1 DOWNTO 0) := X"0";
co : OUT STD_LOGIC := '0'
);
END full_adder_Nbit;
ARCHITECTURE b OF full_adder_Nbit IS
BEGIN
p0 : PROCESS(ci, a, b)
VARIABLE
result_v : UNSIGNED (0 TO N+1);
BEGIN
result_v := ('0' & a & '1') + ('0' & b & ci);
co <= result_v(0);
s <= result_v(1 TO N);
END PROCESS p0;
END b;
I have
question1 : When i write initial value for UNSIGNED like ...
:= "0" without prepand symbol 'X' ModelSim unable to start simulation (Error loading design and point to line number for port a). Which symbols allowed at the beggining?
I think the code above can synthesis any combinatoral adder. I want some that work with clocking.
question 2: why i reinvent adders, is there any class of ready function, where i can read about?
question 3: If i instatiate my entity I am not sure about the length of
result_v variable which
n will be substituted.
Thx in advance.