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Altera_Forum
Honored Contributor
Honored ContributorNeed advice about coding style
Hello I'm Alex and I am novice for VHDL coding. if my english awful pls forgive me. I trying to understand VHDL PROCESS statement. I try with 1bit full adder with carry save function in Quartus2 v...
Altera_ForumHonored Contributor
Honored ContributorOk. I know how to use UNSIGNED ports. I make an example:
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY full_adder_Nbit IS
GENERIC (
N : POSITIVE := 4
);
PORT (
ci : IN STD_LOGIC := '0';
a : IN UNSIGNED (N-1 DOWNTO 0) := X"0";
b : IN UNSIGNED (N-1 DOWNTO 0) := X"0";
s : OUT UNSIGNED (N-1 DOWNTO 0) := X"0";
co : OUT STD_LOGIC := '0'
);
END full_adder_Nbit;
ARCHITECTURE b OF full_adder_Nbit IS
BEGIN
p0 : PROCESS(ci, a, b)
VARIABLE
result_v : UNSIGNED (0 TO N+1);
BEGIN
result_v := ('0' & a & '1') + ('0' & b & ci);
co <= result_v(0);
s <= result_v(1 TO N);
END PROCESS p0;
END b;
