multiple constant drivers error

This is because you can't drive one net (etat_suiv) in two concurrent processes. This is the same as trying to drive one output by two different wires.

What are you trying to do?

thanks for your answer!

I try to run a protocol of LCD display activation. The first process his a clock ( whitch is in an other vhdl file) who temporizing the step of activationof the second process which is a chronology of the event (send the bit to LCD).

And it's this constant who link the two process.

So what can i do for debug that ?

If I understand clearly what you mean, you have a state machine (described by the case instruction block) that you want to evolve on the rising edge of the clock signal.

If this is what you want, you must make only one process depending on clock. In this process, you start by

if rising_edge(clock) then

And inside this if, you put you case instruction block.

Hope this helps.

yes but if I do that, at the first clock event ( high front) all the block will be running at the same time. And I want that the block will running block after block.

But after your first post I try to mix the two process like that :

I delete first process and I put the clock event line in the second:

Process(etat_pres,etat_suiv, SW(0))
begin
if(clock'event and clock = '1') then etat_suiv <= etat_pres;
end if;
case etat_pres is
		
	when ....

and the compilation done sucessfull ( now i go to send the compilation on the FPGA )

--- Quote Start ---

And I want that the block will running block after block.

--- Quote End ---

What do you mean? Which blocks? The blocks in your CASE statements are mutually exclusive because etat_pres can't take 2 values at one time. So what's the problem.

Is it the first time you are writing some VHDL code?

Indeed I don't have a very long experience in VHDL language.

I go to try your idea...

Hello,

I think your design is nearly correct. But when you assign etat_suiv (next_state) in the combinational case construct, then you must assign etat_pres (current_state) in the clock synchronous process:

process (clk)
begin
if rising_edge(clock) then 
  etat_pres <= etat_suiv;
end if;
end process;

Personally, I prefer more simple state machine constructs inside a single clock synchronous process (Mealey type), but that's a matter of taste, I believe.

Regards,

Frank

Thanks for help !

The code of the post# 5 work but stop at the first When ...

So I go to try with the two first process but with the Frank's architecture.

NB: etat_pres = curent statement

etat_suiv = next statement

So what's right?

etat_pres <= etat_suiv;

or

etat_suiv<= etat_pres ;

When I had this process

Process(clock)
begin
  if rising_edge(clock) then 
  etat_suiv <= etat_pres;
end if;
end process;

I get the same error ( multiple constant drivers)

and when I had this

Process(clock)
begin
  if rising_edge(clock) then 
  etat_pres <= etat_suiv;
end if;
end process;

no error but the code dont take effect.

In clock synchronous process, you assign the state, that's in effect in the next clock cycle,

in other words the previously evaluated "next state" gets the new "current state".

etat_pres <= etat_suiv;

P.S.: So far wie dicussed syntactical correctness. There may be other reasons, why the states you expected aren't seen in your design. If they are unreachable by design, you would get a warning and the respective code isn't synthesized. But it can also be a matter of input conditions. How do you debug your design?

Frank

ok and for the case:

case etat_pres is

or

case etat_suiv is

?