multiple constant drivers error

In clock synchronous process, you assign the state, that's in effect in the next clock cycle,

in other words the previously evaluated "next state" gets the new "current state".

etat_pres <= etat_suiv;

P.S.: So far wie dicussed syntactical correctness. There may be other reasons, why the states you expected aren't seen in your design. If they are unreachable by design, you would get a warning and the respective code isn't synthesized. But it can also be a matter of input conditions. How do you debug your design?

Frank