Hi, I open this thread because I have an error on Quartus II (web edition) and I can't finf how debug them. error name: " can't resolve multiple constant drivers for net "etat_suiv.ecriture1" at file *** " So I need some help to debug the situation. the architecture code is : architecture Struct_LCD of LCD is type ETAT is ( ECRITURE1,ECRITURE2,ECRITURE3,ECRITURE4,VALIDATION1,VALIDATION2,VALIDATION3,VALIDATION4); Signal etat_pres, etat_suiv : ETAT := ECRITURE1; begin Process(clock) begin if(clock'event and clock = '1') then etat_suiv <= etat_pres; end if; end process; Process(etat_pres) begin case etat_pres is when ECRITURE1 => LCD_ON<='1'; LCD_Data <= x"30"; LCD_EN <= '1' ; etat_suiv <=VALIDATION1; --if I delete the previous line the error disapear but the code dont work properly. when VALIDATION1 => LCD_EN <= '0' ; etat_suiv <=ECRITURE2; ..... ... Thanks for your answer

This is because you can't drive one net (etat_suiv) in two concurrent processes. This is the same as trying to drive one output by two different wires. What are you trying to do?

thanks for your answer! I try to run a protocol of LCD display activation. The first process his a clock ( whitch is in an other vhdl file) who temporizing the step of activationof the second process which is a chronology of the event (send the bit to LCD). And it's this constant who link the two process. So what can i do for debug that ?

If I understand clearly what you mean, you have a state machine (described by the case instruction block) that you want to evolve on the rising edge of the clock signal. If this is what you want, you must make only one process depending on clock. In this process, you start by if rising_edge(clock) then And inside this if, you put you case instruction block. Hope this helps.

yes but if I do that, at the first clock event ( high front) all the block will be running at the same time. And I want that the block will running block after block. But after your first post I try to mix the two process like that : I delete first process and I put the clock event line in the second: Process(etat_pres,etat_suiv, SW(0)) begin if(clock'event and clock = '1') then etat_suiv <= etat_pres; end if; case etat_pres is when .... and the compilation done sucessfull ( now i go to send the compilation on the FPGA )

--- Quote Start --- And I want that the block will running block after block. --- Quote End --- What do you mean? Which blocks? The blocks in your CASE statements are mutually exclusive because etat_pres can't take 2 values at one time. So what's the problem. Is it the first time you are writing some VHDL code?

multiple constant drivers error | Altera Community

18 Replies

Altera_Forum
Honored Contributor
18 years ago
This has been correct, if not I had mentioned it. The next state is evaluated depending on current state:
case etat_pres is
Altera_Forum
Honored Contributor
18 years ago
Ok thanks, I agree with you; and I havn't the constant drivers error BUT,
in "tools/netlist viewer/state machine viewer"
I get somthing which is suspect. I try with only 3 states and I saw that the "when" in my case dont stop. That's make a big looping which never stop.

the code:
architecture Struct_LCD of LCD is type ETAT is (RESET,ECRITURE1,ECRITURE2); Signal etat_pres, etat_suiv : ETAT := RESET; begin Process(clock) begin if(clock'event and clock = '1') then etat_pres <= etat_suiv; end if; end process; Process(etat_pres,etat_suiv) begin case etat_pres is when RESET => LCD_ON<='1'; etat_suiv <=ECRITURE1; when ECRITURE1 => LCD_EN<= '1'; LCD_ON<='1'; LCD_Data <= x"01"; etat_suiv <=ECRITURE2; when ECRITURE2 => LCD_EN<= '0'; LCD_ON<='1'; LCD_Data <= x"01"; end case; end process; end Struct_LCD ;

and the diagramm is:

http://img167.imageshack.us/img167/4314/lcd0rz0.th.jpg (http://img167.imageshack.us/my.php?image=lcd0rz0.jpg)

and I want:

http://img441.imageshack.us/img441/5025/lcd1jg6.th.jpg (http://img441.imageshack.us/my.php?image=lcd1jg6.jpg)

thanks for your help!
Altera_Forum
Honored Contributor
18 years ago
Hello,

--- Quote Start ---
I saw that the "when" in my case dont stop. That's make a big looping which never stop.
--- Quote End ---

That's exactly, what I read from the code. After reset, it cycles between the two states. You won't name it a finite state machine normaly. It's just a one bit binary counter with a reset and an output (LCD_EN) depending on.

If you intend a more complex functionality (most likely), you should define additional input signals, that conditionally enable the state switch, e. g.:

IF input_condition = '1' THEN etat_suiv <=ECRITURE2; END IF;

You can consult the VHDL state machine templates in Quartus HDL editor context menu for an example. Basically, this isn't a matter of HDL coding rather than how you define your design's functionality.

Regards,
Frank
Altera_Forum
Honored Contributor
18 years ago
ok !

and could I use the clock event in a if, inside the sate ?

IF (clock = '1') THEN
etat_suiv <=ECRITURE2;
END IF;
Altera_Forum
Honored Contributor
18 years ago
Hello,

according to the overall structure used in your state machine, you should not use clock in the combinational process block. Most likely, it causes different behaviour than intended.

It's possible however to combine the two processes into one, as done with the state machine examples in the VHDL templates, where no next_state signal is used. I fear, the different state machine styles used in HDL textbooks and literature examples are somewhat confusing.

Perhaps, it would be easier if you could describe the behaviour you are trying to achieve.

Another remark: I omitted the "hold present state" ELSE condition, that is normally used.

IF input_condition = '1' THEN etat_suiv <=ECRITURE2; ELSE etat_suiv <=ECRITURE1; END IF;

Regards,
Frank
Altera_Forum
Honored Contributor
18 years ago
thank you very much for the help!

I restart a new code with a basic structur using LED to show the different state and it's works ! ( with our architechtur )

Now I want to send to a LCD display a part of bits. This code will initialise the lcd and display one letter on screen.

For this I use an Altera board DE2 but when I run the code ( I can see that the state works with the led ) but the demo word stay on the LCD ( "welcome on altera board" ) but I have initialised like in the LCD data sheet with ON/OFF and the word dont want to disapear.

In datasheet it's say: reset of the display will get with a ON/OFF

So if somone have an idea for this trouble I will be very gracefully.
Altera_Forum
Honored Contributor
18 years ago
Hello,

I've been using similar displays (HD44780 controller type) with microprocessors, but not yet with FPGA. I think, there are many ways to get it non-operating, but I don't see a particular favourite. Are you sure, the interface timining is correct. After reset, some instructions must be used with long wait periods, also in normal operation, the interface is rather slow compared to FPGA standards.

Regards,
Frank
Altera_Forum
Honored Contributor
18 years ago
my last code work with only LED but when I add "LCD_ON='1' the compilation done but in reality the code do nothing correctly. The state will be lauch by two and the lcn dont want to shut down.
So I will try with an other method using only ROM and clock...

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multiple constant drivers error

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