multiple constant drivers error

Hello,

according to the overall structure used in your state machine, you should not use clock in the combinational process block. Most likely, it causes different behaviour than intended.

It's possible however to combine the two processes into one, as done with the state machine examples in the VHDL templates, where no next_state signal is used. I fear, the different state machine styles used in HDL textbooks and literature examples are somewhat confusing.

Perhaps, it would be easier if you could describe the behaviour you are trying to achieve.

Another remark: I omitted the "hold present state" ELSE condition, that is normally used.

IF input_condition = '1' THEN
  etat_suiv <=ECRITURE2;
ELSE
  etat_suiv <=ECRITURE1;
END IF;

Regards,

Frank