Forum Discussion
Altera_Forum
Honored Contributor
18 years agoHello,
--- Quote Start --- I saw that the "when" in my case dont stop. That's make a big looping which never stop. --- Quote End --- That's exactly, what I read from the code. After reset, it cycles between the two states. You won't name it a finite state machine normaly. It's just a one bit binary counter with a reset and an output (LCD_EN) depending on. If you intend a more complex functionality (most likely), you should define additional input signals, that conditionally enable the state switch, e. g.:IF input_condition = '1' THEN
etat_suiv <=ECRITURE2;
END IF; You can consult the VHDL state machine templates in Quartus HDL editor context menu for an example. Basically, this isn't a matter of HDL coding rather than how you define your design's functionality. Regards, Frank