multiple constant drivers error

Hello,

I think your design is nearly correct. But when you assign etat_suiv (next_state) in the combinational case construct, then you must assign etat_pres (current_state) in the clock synchronous process:

process (clk)
begin
if rising_edge(clock) then 
  etat_pres <= etat_suiv;
end if;
end process;

Personally, I prefer more simple state machine constructs inside a single clock synchronous process (Mealey type), but that's a matter of taste, I believe.

Regards,

Frank