Modifying PRBS Frequency in Stratix V

Hello! I have a question while reviewing the approach to validating Bit Error Rate using PRBS with Stratix V.

The purpose of my inquiry is to change the frequency of the transmitted data, and I need clarification on modifications required in the existing code written by the previous developer.

In the first code, the .sdc file specifies a clock frequency of 644.53125MHz through the C64453mhz variable.

In the second code, the refclk_in_clk of the low_latency_10G_1ch module in the .v file is configured to operate with the previously specified C64453mhz.

If I want to change the frequency, is it sufficient to modify the value of the C64453mhz variable in the .sdc file and then compile?

Will there be any issues if I set the frequency to 6GHz or similar? Alternatively, are there specific allowable values for this variable?

Please provide additional code or information if necessary.

============== Coding ==============

.sdc

create_clock -period 100MHz [get_ports {C100mhz}]
create_clock -period 644.53125MHz [get_ports {C64453mhz}]
create_clock -name {altera_reserved_tck} -period 100 [get_ports {altera_reserved_tck}]
create_clock -period 100MHz [get_keepers {*alt_xcvr_reconfig_dfe_sv:dfe_sv|alt_xcvr_reconfig_dfe_cal_sv:inst_xreconfig_cal|dfe_calibrator_sv:inst_calibrator*|alt_cal_edge_detect:inst_edge_detect|alt_edge_det_ff1}]
derive_pll_clocks -create_base_clocks

.v

module gx_link_test_example (

input wire C64453mhz,
input wire C100mhz,

input  wire GXB_RXL11,
output wire GXB_TXL11
);

wire tx_ready;
wire rx_ready;
wire pll_locked;
wire reconfig_busy;

   wire [7:0]    system_reset_cnt;
   reg    system_reset=1'b0;

    // Reset Counter to give active high reset to enable offset cancellation
counter_128 cnt_128_isnt (
.clock (C100mhz),
.q (system_reset_cnt)
);


    always @ (posedge C100mhz)
    begin
       if (system_reset_cnt >= 8'd128)
           begin
              system_reset <= 1'b1;
           end      
    end

low_latency_10g_1ch DUT (
.refclk_in_clk (C64453mhz),
.clk_50_clk (C100mhz), 
.refclk_reset_reset_n (system_reset),
.clk_50_reset_reset_n (system_reset),
.xcvr_low_latency_phy_0_tx_serial_data_export (GXB_TXL11),
.xcvr_low_latency_phy_0_rx_serial_data_export (GXB_RXL11),
.xcvr_low_latency_phy_0_tx_ready_export (tx_ready),       
.xcvr_low_latency_phy_0_rx_ready_export        (rx_ready),       
.xcvr_low_latency_phy_0_pll_locked_export (pll_locked),
.alt_xcvr_reconfig_0_reconfig_busy_reconfig_busy (reconfig_busy)
);
// 1ch passing 30/9/2011

endmodule