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DeadEnd's avatar
DeadEnd
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2 years ago
Solved

Modifying PRBS Frequency in Stratix V

Hello! I have a question while reviewing the approach to validating Bit Error Rate using PRBS with Stratix V. The purpose of my inquiry is to change the frequency of the transmitted data, and I nee...
Hdl
Timing
  • Kshitij_Intel's avatar
    Kshitij_Intel
    2 years ago

    Hi Junsu,

    I have explored and gone through your design, it seems currently 644.53125MHz is coming from an external source pin. If yes, then is it possible to change that clock? I don’t think. Currently you are using clock source of 625MHz which is fed as refclk to XCVR IP. So, if you change the clock accordingly you need to configure the clock source as well. Also, you need to change the Low Latency PHY Intel FPGA IP Configuration accordingly.

    If you any questions or want to discuss further, please let me know we can have a call to discuss.


    Thank you,

    Kshitij Goel


Kshitij_Intel's avatar
Kshitij_Intel
Icon for Frequent Contributor rankFrequent Contributor
2 years ago

Hi Junsu,

I have explored and gone through your design, it seems currently 644.53125MHz is coming from an external source pin. If yes, then is it possible to change that clock? I don’t think. Currently you are using clock source of 625MHz which is fed as refclk to XCVR IP. So, if you change the clock accordingly you need to configure the clock source as well. Also, you need to change the Low Latency PHY Intel FPGA IP Configuration accordingly.

If you any questions or want to discuss further, please let me know we can have a call to discuss.


Thank you,

Kshitij Goel