ModelSim Exit code 211 with CycloneV Fractional PLL

Question

Hello,I'm trying to simulate on ModelSim Intel-FPGA Started Edition 10.5b a design that was compiled on Quartus Prime 18.1 on the CycloneV. The design compiles correctly, and the EDA netlist Writer functions correctly.On modelsim I run the project.do file automatically generated by the netlist writer with the command:do name_project_vhdl.doNext, when I try to simulate it with the command:vsim entity_name ModelSim crashes with exit code 211 (segmentation fault).This seems to happen only when the testbench generated name_project.vho has a cyclonev_fractional_pll. Without it, the project simulates correctly.Is there a way to include cyclonev_fractional_pll without this segmentation fault? Or am I doing something wrong? Thank you.P.S. I already tried to include the verilog version of the CycloneV library by usingvlog .../eda/sim_lib/cyclonev_atoms.v -work cyclonev_verand then running the commandvsim entity_name -L work -L cyclonev_verThis gives me the same fault

richardt_altera · Answer

Could you try to run the simulation using the Nativelink simulation flow?

Additionally, could you try using Questa Intel FPGA edition (starter/non starter) as Modelsim has been replaced by it.

If the issue still persists, could you share the project and testbench so I could try to duplicate the issue and find a solution.

Regards,

Richard Tan

fabrizio_salerno · Answer

Hi Richard,Thanks for the reply.I have attempted to run the same project on Questa Intel FPGA started edition 2023.3  for the Quartus 2023.1 without success (I get error message "Error $MODEL_TECH/../intel/vhdl/src/cyclonev/mentor/cyclonev_atoms_ncrypt.v(38): in protected region" which means the command vsim name does not work.I think I tried the simulation flow you've asked without any success.I'll attach a very simple project which seems to give me these issues (it's a simple PLL with 3 output clocks). The problematic file is in Simple_PLL/simulation/modelsim/e_Simple_PLL.vho, in particular the entity mapped in line 261 is the one that makes Modelsim crash.

richardt_altera · Answer

Are you trying to run RTL simulation or gate-level simulation?

I do not see a testbench in the zip file provided.

We do not usually use gate-level simulation. We recommend that you verify your design using RTL simulation for functionality check and use the Timing analyzer for timing.

Regards,

Richard Tan

fabrizio_salerno · Answer

Hi Richard,

I am trying to do Gate level simulations.

I was unaware that another testbench had to be made, so I made one which simply instantiates the PLL and tries to make a clock. RTL simulation seems to work fine, gate-level simulation gives me the famous crash with error code 211.

Is there any possibility of doing gate-level simulation?

I've attached the project folder with the testbench included in simulation/modelsim/tb.vhd. The commands I run on Modelsim are in order:

do e_Simple_PLL_run_msim_gate_vhdl.do
vcom tb.vhd
vsim e_tb.

This gives me the error code 211. If instead i use e_Simple_PLL_run_msim_rtl_vhdl.do, the simulation works.

richardt_altera · Answer

I am able to run gate-level functional simulation using Questa Intel FPGA with 22.1std version.

Could you try to install Quartus 22.1std and Questa Intel FPGA (or the latest 23.1std version), and run it.

Regards,

Richard Tan

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ModelSim Exit code 211 with CycloneV Fractional PLL

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