Info: Start Nativelink Simulation process

========= EDA Simulation Settings =====================

Sim Mode              :  Gate
Family                :  cyclonev
Quartus root          :  c:/intelfpga_lite/18.1/quartus/bin64/
Quartus sim root      :  c:/intelfpga_lite/18.1/quartus/eda/sim_lib
Simulation Tool       :  modelsim-altera
Simulation Language   :  vhdl
Version               :  93
Simulation Mode       :  GUI
Sim Output File       :  e_Simple_PLL.vho
Sim SDF file          :  e_Simple_PLL__vhdl.sdo
Sim dir               :  simulation\modelsim

=======================================================

Info: Starting NativeLink simulation with ModelSim-Altera software
Sourced NativeLink script c:/intelfpga_lite/18.1/quartus/common/tcl/internal/nativelink/modelsim.tcl
Warning: File e_Simple_PLL_run_msim_gate_vhdl.do already exists - backing up current file as e_Simple_PLL_run_msim_gate_vhdl.do.bak
Info: Spawning ModelSim-Altera Simulation software 
Info: NativeLink simulation flow was successful
