New Contributor
Super ContributorAre you trying to run RTL simulation or gate-level simulation?
I do not see a testbench in the zip file provided.
We do not usually use gate-level simulation. We recommend that you verify your design using RTL simulation for functionality check and use the Timing analyzer for timing.
Regards,
Richard Tan
New ContributorHi Richard,
I am trying to do Gate level simulations.
I was unaware that another testbench had to be made, so I made one which simply instantiates the PLL and tries to make a clock. RTL simulation seems to work fine, gate-level simulation gives me the famous crash with error code 211.
Is there any possibility of doing gate-level simulation?
I've attached the project folder with the testbench included in simulation/modelsim/tb.vhd. The commands I run on Modelsim are in order:
This gives me the error code 211. If instead i use e_Simple_PLL_run_msim_rtl_vhdl.do, the simulation works.
