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Altera_Forum's avatar
Altera_Forum
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15 years ago

LVDS timing where does it go?

I am putting together a DDR LVDS interface running up to 400MHz with a stratix 3 using true diff drivers.

I am taking 66 bits and then using the ddio block to change it into DDR.

I am also generating the clock using a ddio block clocked from a phase shifted version of the clock used to clock the data. I think this is all correct.

I have setup all my timing scripts etc... and have got sensible results from it for setup and hold slack. I have only one concern with it. I am concerned with the amount of time that is being lost from the margins.

At 400MHz, the ideal data width is 625ps setup slack and 625ps hold slack with the clock centred. Timequest is saying that my setup slack is 383ps and my hold slack is 381ps. I know that the two fundamental loses will be switching time and data/clock routing skew. Does dropping 486ps for these two factors seem resonable?

The true diff driver for stratix 3 has rise/fall of 160ps

Any help you can be would be much appreciated :)

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    To me the 486 ps skew across 66 pins sounds reasonable. Since you are using the DDIO block, the register should be in the IO structure, so routing skew should be minimized. But Clock routing I could see have 200-300 ps of skew easily, then if you have clock jitter on your clock that usually eats 200-250 ps of your margin.

    Pete
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Thanks Pete for your answer.

    Does anyone know if it is possible to split out what the switching time is from timequest's results?

    I think I have worked out the channel to channel data skew is 116ps and that the latching clock skew (due to difference in rising edge and falling edge propagations) is 59ps. The clock uncertainty is 50ps. So is the rest of the missing time just the time to switch the voltage on the output???

    So 261ps?? (486 - 116 - 50 - 59 = 261)

    Thanks for your help in advance :)
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Did you take into account the clock propagation skew? between endpoints.

    IE the Setup and Hold minimums slacks are probably on different pins, and part of this reason would be clock propagation skew.

    I don't know how to break out he switch time out of timing quest, but if you had different output loadings on the pins, that would definitely cause differences as well.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Thanks Pete,

    I am currently considering the interface with no board skew and identical capacitors. Its really an exercise for me to understand where the margin is going before i add the real world on top.