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Altera_Forum's avatar
Altera_Forum
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15 years ago

LVDS timing where does it go?

I am putting together a DDR LVDS interface running up to 400MHz with a stratix 3 using true diff drivers. I am taking 66 bits and then using the ddio block to change it into DDR. I am also...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Thanks Pete for your answer.

Does anyone know if it is possible to split out what the switching time is from timequest's results?

I think I have worked out the channel to channel data skew is 116ps and that the latching clock skew (due to difference in rising edge and falling edge propagations) is 59ps. The clock uncertainty is 50ps. So is the rest of the missing time just the time to switch the voltage on the output???

So 261ps?? (486 - 116 - 50 - 59 = 261)

Thanks for your help in advance :)