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Altera_Forum
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15 years ago

LVDS timing where does it go?

I am putting together a DDR LVDS interface running up to 400MHz with a stratix 3 using true diff drivers. I am taking 66 bits and then using the ddio block to change it into DDR. I am also...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Thanks Pete,

I am currently considering the interface with no board skew and identical capacitors. Its really an exercise for me to understand where the margin is going before i add the real world on top.