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Altera_Forum
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15 years ago

LVDS timing where does it go?

I am putting together a DDR LVDS interface running up to 400MHz with a stratix 3 using true diff drivers. I am taking 66 bits and then using the ddio block to change it into DDR. I am also...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Did you take into account the clock propagation skew? between endpoints.

IE the Setup and Hold minimums slacks are probably on different pins, and part of this reason would be clock propagation skew.

I don't know how to break out he switch time out of timing quest, but if you had different output loadings on the pins, that would definitely cause differences as well.