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Altera_Forum
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15 years ago

LVDS timing where does it go?

I am putting together a DDR LVDS interface running up to 400MHz with a stratix 3 using true diff drivers. I am taking 66 bits and then using the ddio block to change it into DDR. I am also...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

To me the 486 ps skew across 66 pins sounds reasonable. Since you are using the DDIO block, the register should be in the IO structure, so routing skew should be minimized. But Clock routing I could see have 200-300 ps of skew easily, then if you have clock jitter on your clock that usually eats 200-250 ps of your margin.

Pete