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marcorig's avatar
marcorig
Icon for New Contributor rankNew Contributor
1 year ago

LPM DIVIDE behaves differently between simulation and implementation

I have implemented a divider in a custom VHDL module in order to replace the instances of the LPM_DIVIDE IPs in my project. I've then checked the functionality of my module against the LPM_DIVIDE and...
Compilation
Platform
Simulation
ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
1 year ago

Hi,


I observe that if change pipeline number, the signal tap results will be different.

I suspect is the timing issue. Could you add .sdc file to check is that the timing pass? Make sure the timing is pass.


Thanks,

Regards,

Sheng