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marcorig's avatar
marcorig
Icon for New Contributor rankNew Contributor
1 year ago

LPM DIVIDE behaves differently between simulation and implementation

I have implemented a divider in a custom VHDL module in order to replace the instances of the LPM_DIVIDE IPs in my project. I've then checked the functionality of my module against the LPM_DIVIDE and...
Compilation
Platform
Simulation
ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
1 year ago

Hi,

For signal tap, i can get the same result as you.

However for simulation, i use your testbench and modelsim but i can't get the same result as you check attached pic. It keeps the same at FFFFFFEC78000000. Is there anything i miss?

Thanks,

Regards,

Sheng