load .mif-file on DE0-CV board

Hello

Hello Johi,

TO_BE_DONE

and this is my memory-code:

LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY MBDMemory IS
	PORT
	(
		data			: IN STD_LOGIC_VECTOR (5 DOWNTO 0);
		inclock		: IN STD_LOGIC  := '1';
		outclock		: IN STD_LOGIC ;
		rdaddress	: IN STD_LOGIC_VECTOR (5 DOWNTO 0);
		wraddress	: IN STD_LOGIC_VECTOR (5 DOWNTO 0);
		wren			: IN STD_LOGIC  := '0';
		q				: OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
	);
END MBDMemory;
ARCHITECTURE SYN OF mbdmemory IS
	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (5 DOWNTO 0);
BEGIN
	q    <= sub_wire0(5 DOWNTO 0);
	altsyncram_component : altsyncram
	GENERIC MAP (
		address_aclr_b => "NONE",
		address_reg_b => "CLOCK0",
		clock_enable_input_a => "BYPASS",
		clock_enable_input_b => "BYPASS",
		clock_enable_output_b => "BYPASS",
		intended_device_family => "Cyclone V",
		lpm_type => "altsyncram",
		numwords_a => 64,
		numwords_b => 64,
		operation_mode => "DUAL_PORT",
		outdata_aclr_b => "NONE",
		outdata_reg_b => "CLOCK1",
		power_up_uninitialized => "FALSE",
		read_during_write_mode_mixed_ports => "OLD_DATA",
		widthad_a => 6,
		widthad_b => 6,
		width_a => 6,
		width_b => 6,
		width_byteena_a => 1
	)
	PORT MAP (
		address_a => wraddress,
		address_b => rdaddress,
		clock0 => inclock,
		clock1 => outclock,
		data_a => data,
		wren_a => wren,
		q_b => sub_wire0
	);
END SYN;

Hello Johi,

architecture behavior of MemoryBasedDesign is
		type mif_file_type is array(0 to 64*6) of bit_vector(5 downto 0);
		signal mif_file : mif_file_type;
		attribute mif_file_init_file : string;
		attribute mif_file_init_file of mif_file : signal is "mif_file.mif";
		--VERILOG:
		--Bitmap font:
		(* mif_file_init_file = "mif_file.mif" *) reg  mif_file;
	-- wrapper
	component MBDMemory
		port(	data			: IN STD_LOGIC_VECTOR (5 DOWNTO 0);
				inclock		: IN STD_LOGIC  := '1';
				outclock		: IN STD_LOGIC ;
				rdaddress	: IN STD_LOGIC_VECTOR (5 DOWNTO 0);
				wraddress	: IN STD_LOGIC_VECTOR (5 DOWNTO 0);
				wren			: IN STD_LOGIC  := '0';
				q				: OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
			);
	end component;

and here is my mif-file:

DEPTH = 64;             % Memory depth and width are required %
WIDTH = 6;              % Enter a decimal number %
ADDRESS_RADIX = HEX; % Address and value radixes are optional %
DATA_RADIX = HEX;     % Enter BIN, DEC, HEX, or OCT; unless %
CONTENT
BEGIN
     : 0000; % Range--Every address from 00 to 3F = 0000 %
    00 : 0x22;
    01    : 000011;
    02    : 22;
    03    : 0x22;
    04    : 0x22;
    05    : 0x22;
END ;

Okay, here a short update how I solved the problem if somebody got similar problems as I had.

DEPTH = 64; % Memory depth and width are required %WIDTH = 6; % Enter a decimal number %
ADDRESS_RADIX = HEX; % Address and value radixes are optional %
DATA_RADIX = HEX; % Enter BIN, DEC, HEX, or OCT; unless %
CONTENT
BEGIN
 : 0000; % Range--Every address from 00 to FF = 0000 %
00 : 0; -- to get the value '0' to the memory location 0
01 : 1; -- to get the value '1' to the memory location 1
02 : A; -- to get the value '0xA' to the memory location 2
... continue this way
END ;

-- wrapper
    component MBDDesignMemoryMif
        port(    data            : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
                inclock        : IN STD_LOGIC  := '1';
                outclock        : IN STD_LOGIC ;
                rdaddress    : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
                wraddress    : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
                wren            : IN STD_LOGIC  := '0';
                q                : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
            );
    end component;

uut: MBDDesignMemoryMif
        port map(data             => WriteData,
                    inclock         =>    clock_10hz_int,
                    outclock     =>    clock_10hz_int,
                    rdaddress     =>    ReadAddress,
                    wraddress    =>    WriteAddress,
                    wren             =>    WriteEN,
                    q                 =>    ReadData
                    );