Forum Discussion
Altera_Forum
Honored Contributor
9 years agoHello Johi,
thanks for your help! Unfortunately now the project doesn't even want to compile. I tried to write your code (of course modified) at different places but it didn't work. Here is the modified part of my code:architecture behavior of MemoryBasedDesign is
type mif_file_type is array(0 to 64*6) of bit_vector(5 downto 0);
signal mif_file : mif_file_type;
attribute mif_file_init_file : string;
attribute mif_file_init_file of mif_file : signal is "mif_file.mif";
--VERILOG:
--Bitmap font:
(* mif_file_init_file = "mif_file.mif" *) reg mif_file;
-- wrapper
component MBDMemory
port( data : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
inclock : IN STD_LOGIC := '1';
outclock : IN STD_LOGIC ;
rdaddress : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
wraddress : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
wren : IN STD_LOGIC := '0';
q : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
);
end component; Can you see where the problem is? Best, orPoG