Forum Discussion
Altera_Forum
Honored Contributor
9 years agoOkay, here a short update how I solved the problem if somebody got similar problems as I had.
1. to include the mif-file to the memory you need to create this one first and then create the memory. During the creationprocess of the memory with the Megawizard it's possible to include a Mif-file. On this way you get your memory with the desired values. The code for the Mif file is the following:DEPTH = 64; % Memory depth and width are required %WIDTH = 6; % Enter a decimal number %
ADDRESS_RADIX = HEX; % Address and value radixes are optional %
DATA_RADIX = HEX; % Enter BIN, DEC, HEX, or OCT; unless %
CONTENT
BEGIN
: 0000; % Range--Every address from 00 to FF = 0000 %
00 : 0; -- to get the value '0' to the memory location 0
01 : 1; -- to get the value '1' to the memory location 1
02 : A; -- to get the value '0xA' to the memory location 2
... continue this way
END ; 2. to wrap two vhdl-files together (in this case the memory file, created with the Megawizard, and the main file), you need to write the following code into the main vhdl file: This part is placed directly after the 'architecture xx of yy is', before the 'begin'. (like the signals) -- wrapper
component MBDDesignMemoryMif
port( data : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
inclock : IN STD_LOGIC := '1';
outclock : IN STD_LOGIC ;
rdaddress : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
wraddress : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
wren : IN STD_LOGIC := '0';
q : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
);
end component; This part is placed after the 'begin' of the architecture: uut: MBDDesignMemoryMif
port map(data => WriteData,
inclock => clock_10hz_int,
outclock => clock_10hz_int,
rdaddress => ReadAddress,
wraddress => WriteAddress,
wren => WriteEN,
q => ReadData
); All the shown code parts in this post belong and work with the variables of my project, which I already posted in this thread. Hopefully I can help somebody with this ;)