It is annoying the VHDL support in Quartus gets worse and worse

Generating and maintaining complicated cores in 2 languages has never happened, and will never happen in the future. Altera now do all their new cores in SystemVerilog, so if you ask for VHDL you will only get a wrapper at best. And this is compounded again by the fact that free modelsim that ships with Q15 supports dual language (probably because of these issues).

VHDL is a language loosing support. It just does not have the industry support anymore that Verilog/SV have now got, plus lacks many verification features you get for free in SV, and dont even think about UVM.

To be honest, if you are fluent in VHDL, you should be able to read Verilog pretty easily, and learning it is not very hard (Verilog to VHDL is harder).

If you have any specific issues, you need to raise enhancement requests with altera.

Altera's VHDL is far better than Xilinx.

) it is quite the same like situation with browser in old Windows OS. Why only Internet Explorer ?

in VHDL for test you can put assert operator, and making testbench in VHDL is also easy.

perhaps it is compile time needed to verilog and VHDL program. I believe Verilog is more close to hardware architecture than VHDL in the manner it used.

If you remember the time for compile or even only analysis and synthesis in MaxPlus and compare it with Quartus ... no comment

I wonder if openCL program in C supersede Verilog.

Just my opinion

Verilog has the same capabilities as VHDL, and then many more. Thinks like classes make verification in SV so much easier. A few asserts does not make a complete testbench. And if all your verification capabilities, re-use libraries and engineers all use SV, why bother teaching them VHDL also?

Verilog and VHDL are on a par when it comes to similarities to hardware.

Bring MaxPlus into the argument doesnt really help - Its 15 years old and no longer relavent.

I think OpenCL and C->HDL will become more prevelent as designs get more complicated. The time to get an OpenCL design working is potentially faster than RTL, although not as optimised, but for some, they dont care about optimisation.

So it all depends what teammates know.

OpenCL support is absent in Quartus Lite version though.

What about code generated for IP - it doesn't matter if you consider IP as blackbox.

HDL should be read high definition language for hardware design. but for now it is not ;)