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Altera_Forum's avatar
Altera_Forum
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10 years ago

It is annoying the VHDL support in Quartus gets worse and worse

Why does the VHDL support from Altera keep getting worse? I keep bumping into IP generated VHDL files that that is just poorly made and in which case I have to use the Verilog generated files. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

So it all depends what teammates know.

OpenCL support is absent in Quartus Lite version though.

What about code generated for IP - it doesn't matter if you consider IP as blackbox.

HDL should be read high definition language for hardware design. but for now it is not ;)