It is annoying the VHDL support in Quartus gets worse and worse

Generating and maintaining complicated cores in 2 languages has never happened, and will never happen in the future. Altera now do all their new cores in SystemVerilog, so if you ask for VHDL you will only get a wrapper at best. And this is compounded again by the fact that free modelsim that ships with Q15 supports dual language (probably because of these issues).

VHDL is a language loosing support. It just does not have the industry support anymore that Verilog/SV have now got, plus lacks many verification features you get for free in SV, and dont even think about UVM.

To be honest, if you are fluent in VHDL, you should be able to read Verilog pretty easily, and learning it is not very hard (Verilog to VHDL is harder).

If you have any specific issues, you need to raise enhancement requests with altera.

Altera's VHDL is far better than Xilinx.