It is annoying the VHDL support in Quartus gets worse and worse

Verilog has the same capabilities as VHDL, and then many more. Thinks like classes make verification in SV so much easier. A few asserts does not make a complete testbench. And if all your verification capabilities, re-use libraries and engineers all use SV, why bother teaching them VHDL also?

Verilog and VHDL are on a par when it comes to similarities to hardware.

Bring MaxPlus into the argument doesnt really help - Its 15 years old and no longer relavent.

I think OpenCL and C->HDL will become more prevelent as designs get more complicated. The time to get an OpenCL design working is potentially faster than RTL, although not as optimised, but for some, they dont care about optimisation.