It is annoying the VHDL support in Quartus gets worse and worse

) it is quite the same like situation with browser in old Windows OS. Why only Internet Explorer ?

in VHDL for test you can put assert operator, and making testbench in VHDL is also easy.

perhaps it is compile time needed to verilog and VHDL program. I believe Verilog is more close to hardware architecture than VHDL in the manner it used.

If you remember the time for compile or even only analysis and synthesis in MaxPlus and compare it with Quartus ... no comment

I wonder if openCL program in C supersede Verilog.

Just my opinion