Issue with Nested Modules in ModelSim 20.1.1 - Not Following Verilog Rules

Hi Intel Community,

I encountered an issue while testing ModelSim version 20.1.1 (Latest) related to Verilog syntax rules. I am sharing this here to bring it to Intel's attention.I tested the behavior of nested modules in Verilog to check if the tool adheres to Verilog language rules. According to Verilog standards, defining a module inside another module (module within module) is not allowed.

Observations:

1. ModelSim 20.1.1: The simulation runs successfully, producing an output. However, this behavior is incorrect as nested modules are not allowed in Verilog.
2. QuestaSim: When I ran the same code in QuestaSim, it correctly reported the error: "Module 'decoder' is not defined", which is the expected behavior.
3. EDA Playground: On EDA Playground, the simulation explicitly states: "Nested module is not allowed", aligning with Verilog standards.

Please investigate this issue in ModelSim 20.1.1. It seems the tool is not enforcing the Verilog rules for nested modules.

I understand Verilog rules well, and this test was purely conducted to evaluate how ModelSim enforces the language standards.Let me know if you need more details about the test case or if I can assist in further debugging.

Thanks