Issue with Nested Modules in ModelSim 20.1.1 - Not Following Verilog Rules

Hi,

I had tested in both Questa Intel 2024.1 and modelsim 2020.1, both can run the simulation.

Questa Intel 2024.1 screenshot:

modelsim 2020.1 screenshot:

I think can be run in simulator tool but not in synthesis tool.

Simulation tools are more permissive about the syntax and constructs used because they only need to simulate the design and do not need to map it onto actual hardware.

Synthesis tools map Verilog code onto physical hardware. They have stricter requirements.

Thanks,

Regards,

Sheng