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aprilsohail's avatar
aprilsohail
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1 year ago

Issue with Nested Modules in ModelSim 20.1.1 - Not Following Verilog Rules

Hi Intel Community, I encountered an issue while testing ModelSim version 20.1.1 (Latest) related to Verilog syntax rules. I am sharing this here to bring it to Intel's attention.I tested the behav...
Simulation
ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
1 year ago

Hi,


Possible to provide the test files? and I'll report this to internal engineering team


Thanks,

Regards,

Sheng


    • FvM's avatar
      FvM
      Icon for Super Contributor rankSuper Contributor
      1 year ago
      Hi,
      Modelsim has syntax level settings per source file. Syntax may be set to SystemVerilog despite of .v file type.

      Apart from this point, Modelsim isn't a formal verification tool. I'm not sure if accepting certain language constructs beyond selected syntax level should be considered as bug. On the other side, you can't be sure that all Verilog or SV constructs are understood by a specific Quartus version, you need to check the language support specs.
      Regards
      Frank
      • aprilsohail's avatar
        aprilsohail
        Icon for New Contributor rankNew Contributor
        1 year ago
        A basic verilog compiler should not allow nested modules, but here is not basic verilog compiler , it is from world's renowned company