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Sakib's avatar
Sakib
Icon for New Contributor rankNew Contributor
2 months ago

Issue with MIPI CSI2 Encrypted IP File During Project Integration

Hi, I am working on a project where I have integrated two separate projects into a single top-level design. Project A includes the MIPI CSI2 IP and other related components. Project B contains the...
Compilation
Hdl
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BCuze's avatar
BCuze
Icon for Occasional Contributor rankOccasional Contributor
2 months ago

I suspect the Altera SV code for the fifo isn't optimal (probably missing "logic" in the port declaration).

Note however that while using `default_nettype none was a recommended practice in Verilog, it has become -alas- a bad idea in SystemVerilog. I suggest you remove it in your (wrapper ?) code.