Forum Discussion

Branden_Allen's avatar
Branden_Allen
Icon for New Contributor rankNew Contributor
7 years ago

Is the systemverilog "case inside" statement for definitions of a range of conditions within a case block available for synthesis and, if not, when will this be implemented?

Description

Using the "inside" keyword with a "case" block to enable the definition of ranges for a desired output value in systemverilog code (cf. attached example) synthesis fails on an apparent syntax error.

Result

Error (10170): Verilog HDL syntax error at frontend_ifc.sv(370) near text: "inside"; expecting an operand

Software Details

Quartus Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition

case(stage) inside
	[0:20]: begin
		clkon<= 0;
	end
 
	21: begin
		clkon<= 1;
	end
 
	default: begin
		stage<= 0;
	end
endcase

5 Replies

  • Vicky1's avatar
    Vicky1
    Icon for Regular Contributor rankRegular Contributor
    7 years ago

    Hi,

    'case inside' is not supported in Quartus, only 'unique/priority support available on case statements

    Quartus text editor recognizes it as a key word (it shows up in blue color).

    refer the below attachment,

    Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

    Best Regards

    Vikas Jathar

    (This message was posted on behalf of Intel Corporation)

  • AndyN's avatar
    AndyN
    Icon for Occasional Contributor rankOccasional Contributor
    7 years ago

    As tool support for this sort of thing tends to be based on user demand, I'd just like to chime in and say that I'd definitely like to see case inside as a feature supported for synthesis in the future. The coding work-arounds to effectively implement this functionality can get really ugly and convoluted when it could otherwise have been expressed in a very concise case inside statement.

    Besides "it hasn't been done yet", is there any technical reason why case inside hasn't been implemented yet?

    Thanks,

    Andy

  • Branden_Allen's avatar
    Branden_Allen
    Icon for New Contributor rankNew Contributor
    7 years ago

    Thanks,

    implementation of this functionality is useful for our code development and would help make Intel parts more attractive for our projects. Is this forum the proper place to make such statements/requests or is there a separate submission point?

    Best,

    Branden

  • Vicky1's avatar
    Vicky1
    Icon for Regular Contributor rankRegular Contributor
    7 years ago

    Hi,

    SystemVerilog has limited support in Intel Quartus tool, please refer the below link to check supported SystemVerilog features in Quartus tool,

    https://www.intel.com/content/www/us/en/programmable/quartushelp/current/index.htm#hdl/vlog/vlog_list_sys_vlog.htm

    @Branden Allen, Refer the below link for 'mySupport' & Try to keep checking for 'What`s New in Intel Quartus Prime Software'.

    https://www.intel.com/content/www/us/en/programmable/support/support-resources/design-software/quartus-ii/sof-quartus.html

    Best Regards

    Vikas Jathar

    (This message was posted on behalf of Intel Corporation)