Is the systemverilog "case inside" statement for definitions of a range of conditions within a case block available for synthesis and, if not, when will this be implemented?

Hi,

'case inside' is not supported in Quartus, only 'unique/priority support available on case statements

Quartus text editor recognizes it as a key word (it shows up in blue color).

refer the below attachment,

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Best Regards

Vikas Jathar

(This message was posted on behalf of Intel Corporation)