Forum Discussion
Branden_Allen
New Contributor
New ContributorIs the systemverilog "case inside" statement for definitions of a range of conditions within a case block available for synthesis and, if not, when will this be implemented?
Description Using the "inside" keyword with a "case" block to enable the definition of ranges for a desired output value in systemverilog code (cf. attached example) synthesis fails on an apparent s...
KhaiChein_Y_Intel
Regular Contributor
Regular ContributorHi,
The Intel Quartus Prime Standard and Lite Edition software have limited System Verilog language support. You may use case instead of case...inside
Thanks.
