Is the systemverilog "case inside" statement for definitions of a range of conditions within a case block available for synthesis and, if not, when will this be implemented?

Hi,

SystemVerilog has limited support in Intel Quartus tool, please refer the below link to check supported SystemVerilog features in Quartus tool,

https://www.intel.com/content/www/us/en/programmable/quartushelp/current/index.htm#hdl/vlog/vlog_list_sys_vlog.htm

@Branden Allen, Refer the below link for 'mySupport' & Try to keep checking for 'What`s New in Intel Quartus Prime Software'.

https://www.intel.com/content/www/us/en/programmable/support/support-resources/design-software/quartus-ii/sof-quartus.html

Best Regards

Vikas Jathar

(This message was posted on behalf of Intel Corporation)