Is the systemverilog "case inside" statement for definitions of a range of conditions within a case block available for synthesis and, if not, when will this be implemented?

As tool support for this sort of thing tends to be based on user demand, I'd just like to chime in and say that I'd definitely like to see case inside as a feature supported for synthesis in the future. The coding work-arounds to effectively implement this functionality can get really ugly and convoluted when it could otherwise have been expressed in a very concise case inside statement.

Besides "it hasn't been done yet", is there any technical reason why case inside hasn't been implemented yet?

Thanks,

Andy