Is the speed determined by fmax or delays?

The longest delay in the design determines the fmax.

But you dont define what you mean by speed? if you mean whats the fastest clock speed you can clock the design at, then both professors are correct.

Hi Tricky,

Thanks for replying to my posts!

Erm by the speed of the circuit I mean how efficient it is in handling arithmetic, how many calculations it does per unit time.

Hope that makes sense.

Cheers,

Chris

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Hi Tricky,

Thanks for replying to my posts!

Erm by the speed of the circuit I mean how efficient it is in handling arithmetic, how many calculations it does per unit time.

Hope that makes sense.

Cheers,

Chris

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Well then thats max clock speed. The faster the clock, the more calculations it can do in a second. The latency wont matter, because it will still be doing 1 calc/clock tick, it will just take longer before Input1 becomes output1.

Normally, the higher the latency, the higher the max clock.

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Well then thats max clock speed. The faster the clock, the more calculations it can do in a second. The latency wont matter, because it will still be doing 1 calc/clock tick, it will just take longer before Input1 becomes output1.

Normally, the higher the latency, the higher the max clock.

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Thanks for your reply again! But don't you mean the lower the latency, the higher the max clock?

Cheers,

Chris

Yes - the slowest register to register latency determines the max clock.

BUT

Usually, to minimise the register to register delays, you increase the number of pipeline steps through the algorithm, which increases the latency of the algorithm as a whole.

Thanks again Tricky.

Forgive my lack of understanding but I still find the following part a bit confusing.

The increase of fmax = more calculations per sec, but also = longer for output to be calculated?

Doesn't the "increase the latency of the algorithm as a whole" part mean that the results come out slower? And doesn't that defeat the purpose of having faster calculations?

Sorry if my questions are being a nuisance.

Thanks a lot,

Chris

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Doesn't the "increase the latency of the algorithm as a whole" part mean that the results come out slower? And doesn't that defeat the purpose of having faster calculations?

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Usually, an algorithm has a pipeline delay so that you get a delay such that:

Input A --- time delay n ---> Output A

But, assuming its a pipeline, 1 clock after Input A, you can input B into the algorithm, and 1 clock after output A, you get output B. Here is a quick diagram that has time increasing left to right:

Ip A  ------- time n    ------> Ouput A
  Ip B  ------- time n    ------> Output B
    Ip C  ------- time n    ------> Output C
      etc.

So at this rate, you get 1 output per clock cycle, so while initially you have to wait a little longer for the output to arrive, once it does arrive you are getting 1 output per clock. If you clock it faster, you get a faster output rate.

Sorry for the late reply but thanks a lot for making it much clearer! But are there conditions where increasing the pipeline depth doesn't increase the fmax, but decreases it instead?

Best regards,

Chris

It is true that delay decides fmax but we need to be more specific what we mean by delay.

For rtl chains fmax is determined by setup time (not hold time of registers).

Tsetup is an inherent nature of clocked flips.

FPGA manufacturers control setup through the reg to reg delay routing such that clk always arrives not later than data. Under this situation Tsetup becomes the primary variable that limits fmax.

better Fmax is achieved If the reg to reg route is not too long. If so break it up by insertin registers.(called pipelining)

However pipelining is a general term that could mean inserting registers for any other purpose. every register introduces one clk period delay before its output appears.