Is the speed determined by fmax or delays?

It is true that delay decides fmax but we need to be more specific what we mean by delay.

For rtl chains fmax is determined by setup time (not hold time of registers).

Tsetup is an inherent nature of clocked flips.

FPGA manufacturers control setup through the reg to reg delay routing such that clk always arrives not later than data. Under this situation Tsetup becomes the primary variable that limits fmax.

better Fmax is achieved If the reg to reg route is not too long. If so break it up by insertin registers.(called pipelining)

However pipelining is a general term that could mean inserting registers for any other purpose. every register introduces one clk period delay before its output appears.