Forum Discussion
Hi @AqidAyman_Intel ,
Thank you for getting back to me, but this response fails to address the issue. It merely attempts in a number of ways to avoid addressing the actual issue.
The issue, again, is that this mode of the IOPLL appears to be grossly broken or not implemented correctly by Quartus.
My design requirements are irrelevant to this discussion, and suggestions to use other modes of the IOPLL are irrelevant. I'm not looking for help with my designs. I'm bringing to your attention the fact that something appears to be broken on the Altera side. That's the issue that needs to be addressed.
Also irrelevant are the registers on the input clock and the resulting synchronous CDC in the example I provided. No, they do not affect the operation of the IOPLL. I put them in the design example merely as a convenient way to observe the problem with the IOPLL, but you can remove them from the design entirely and the problem with the IOPLL still exists just the same.
I'm providing another even simpler design example (attached) that doesn't have those registers on the input clock, so that there are no distractions or red herrings.
Please go back to your internal team for them to really investigate and address the actual problem with this IOPLL mode.
Thanks,
-Roee