minhlee
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New ContributorI/O assignment analysis fail Quartus Prime Lite 23.1 for CycloneV
Hi everyone, currently I am creating my own SoC system. I have run Analysis and Synthesis successfully, then I run tcl script hps_sdram_p0_parameters.tcl and hps_sdram_p0_pin_assignments.tcl respectively. After that, I run I/O assignment analysis and receive this error:
Critical Warning (169085): No exact pin location assignment(s) for 120 pins of 172 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report. Critical Warning (174073): No exact pin location assignment(s) for 1 RUP, RDN, or RZQ pins of 1 total RUP, RDN or RZQ pins Info (174074): RUP, RDN, or RZQ pin HPS_DDR3_RZQ not assigned to an exact location on the device Info (184020): Starting Fitter periphery placement operations Error (14996): The Fitter failed to find a legal placement for all periphery components Error (14986): After placing as many components as possible, the following errors remain: Error (175001): The Fitter cannot place 30 pins. Info (14596): Information about the failing component(s): Info (175028): The pin name(s): HPS_DDR3_DQ[8], HPS_DDR3_DQ[9], HPS_DDR3_DQ[10], HPS_DDR3_DQ[11], HPS_DDR3_DQ[12] and other 25 pins Info (15647): These pins are in a group of 30 components with similar legality requirements Error (16234): No legal location could be found out of 176 considered location(s). Reasons why each location could not be used are summarized below: Error (184016): There were not enough single-ended bidirectional pin locations available (91 locations affected) Info (175029): Y9. Already placed at this location: pin altera_reserved_tdo Info (175015): The I/O pad altera_reserved_tdo is constrained to the location PIN_Y9 due to: JTAG placement Info (14709): The constrained I/O pad is contained within this pin Info (175029): AC7. Already placed at this location: pin altera_reserved_tms Info (175015): The I/O pad altera_reserved_tms is constrained to the location PIN_AC7 due to: JTAG placement Info (14709): The constrained I/O pad is contained within this pin Info (175029): AB5. Already placed at this location: pin altera_reserved_tck Info (175015): The I/O pad altera_reserved_tck is constrained to the location PIN_AB5 due to: JTAG placement Info (14709): The constrained I/O pad is contained within this pin Info (175029): W10. Already placed at this location: pin altera_reserved_tdi Info (175015): The I/O pad altera_reserved_tdi is constrained to the location PIN_W10 due to: JTAG placement Info (14709): The constrained I/O pad is contained within this pin Info (175029): Y8. Already placed at this location: pin HDMI_TX_D[3] Info (175015): The I/O pad HDMI_TX_D[3] is constrained to the location PIN_Y8 due to: User Location Constraints (PIN_Y8) Info (14709): The constrained I/O pad is contained within this pin Info (175029): Y4. Already placed at this location: pin HDMI_TX_D[9] Info (175015): The I/O pad HDMI_TX_D[9] is constrained to the location PIN_Y4 due to: User Location Constraints (PIN_Y4) Info (14709): The constrained I/O pad is contained within this pin Info (175029): W8. Already placed at this location: pin HDMI_TX_D[2] Info (175015): The I/O pad HDMI_TX_D[2] is constrained to the location PIN_W8 due to: User Location Constraints (PIN_W8) Info (14709): The constrained I/O pad is contained within this pin Info (175029): Y5. Already placed at this location: pin HDMI_TX_D[7] Info (175015): The I/O pad HDMI_TX_D[7] is constrained to the location PIN_Y5 due to: User Location Constraints (PIN_Y5) Info (14709): The constrained I/O pad is contained within this pin Info (175029): T8. Already placed at this location: pin HDMI_TX_HS Info (175015): The I/O pad HDMI_TX_HS is constrained to the location PIN_T8 due to: User Location Constraints (PIN_T8) Info (14709): The constrained I/O pad is contained within this pin Info (175029): AB4. Already placed at this location: pin HDMI_TX_D[11] Info (175015): The I/O pad HDMI_TX_D[11] is constrained to the location PIN_AB4 due to: User Location Constraints (PIN_AB4) Info (14709): The constrained I/O pad is contained within this pin Info (175029): AA4. Already placed at this location: pin HDMI_I2C_SDA Info (175015): The I/O pad HDMI_I2C_SDA is constrained to the location PIN_AA4 due to: User Location Constraints (PIN_AA4) Info (14709): The constrained I/O pad is contained within this pin Info (175029): U10. Already placed at this location: pin HDMI_I2C_SCL Info (175015): The I/O pad HDMI_I2C_SCL is constrained to the location PIN_U10 due to: User Location Constraints (PIN_U10) Info (14709): The constrained I/O pad is contained within this pin Info (175029): and 79 more locations not displayed Error (179008): Could not find enough available I/O pin locations that can be configured to use a VCCIO voltage of 2.5V (85 locations affected) Info (175029): U9 Info (175029): V10 Info (175029): AD4 Info (175029): AC4 Info (175029): AA11 Info (175029): AE6 Info (175029): Y11 Info (175029): AD5 Info (175029): AF4 Info (175029): W11 Info (175029): AF7 Info (175029): AH3 Info (175029): and 73 more locations not displayed Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:01 Info (11798): Fitter preparation operations ending: elapsed time is 00:00:18 Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information. Warning (169064): Following 60 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results Info (169065): Pin HDMI_I2S has a permanently disabled output enable Info (169065): Pin HDMI_LRCLK has a permanently disabled output enable Info (169065): Pin HDMI_MCLK has a permanently disabled output enable Info (169065): Pin HDMI_SCLK has a permanently disabled output enable Info (169065): Pin HPS_CONV_USB_N has a permanently disabled output enable Info (169065): Pin HPS_ENET_INT_N has a permanently disabled output enable Info (169065): Pin HPS_ENET_MDIO has a permanently disabled output enable Info (169065): Pin HPS_GSENSOR_INT has a permanently disabled output enable Info (169065): Pin HPS_I2C0_SCLK has a permanently disabled output enable Info (169065): Pin HPS_I2C0_SDAT has a permanently disabled output enable Info (169065): Pin HPS_I2C1_SCLK has a permanently disabled output enable Info (169065): Pin HPS_I2C1_SDAT has a permanently disabled output enable Info (169065): Pin HPS_KEY has a permanently disabled output enable Info (169065): Pin HPS_LED has a permanently disabled output enable Info (169065): Pin HPS_LTC_GPIO has a permanently disabled output enable Info (169065): Pin HPS_SD_CMD has a permanently disabled output enable Info (169065): Pin HPS_SD_DATA[0] has a permanently disabled output enable Info (169065): Pin HPS_SD_DATA[1] has a permanently disabled output enable Info (169065): Pin HPS_SD_DATA[2] has a permanently disabled output enable Info (169065): Pin HPS_SD_DATA[3] has a permanently disabled output enable Info (169065): Pin HPS_SPIM_SS has a permanently disabled output enable Info (169065): Pin HPS_USB_DATA[0] has a permanently disabled output enable Info (169065): Pin HPS_USB_DATA[1] has a permanently disabled output enable Info (169065): Pin HPS_USB_DATA[2] has a permanently disabled output enable Info (169065): Pin HPS_USB_DATA[3] has a permanently disabled output enable Info (169065): Pin HPS_USB_DATA[4] has a permanently disabled output enable Info (169065): Pin HPS_USB_DATA[5] has a permanently disabled output enable Info (169065): Pin HPS_USB_DATA[6] has a permanently disabled output enable Info (169065): Pin HPS_USB_DATA[7] has a permanently disabled output enable Info (169065): Pin HDMI_I2C_SCL has a permanently enabled output enable Info (169065): Pin HPS_DDR3_DQ[8] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQ[9] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQ[10] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQ[11] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQ[12] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQ[13] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQ[14] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQ[15] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQ[16] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQ[17] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQ[18] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQ[19] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQ[20] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQ[21] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQ[22] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQ[23] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQ[24] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQ[25] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQ[26] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQ[27] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQ[28] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQ[29] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQ[30] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQ[31] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQS_N[1] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQS_N[2] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQS_N[3] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQS_P[1] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQS_P[2] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQS_P[3] has a permanently disabled output enable Warning (169069): Following 72 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results Info (169070): Pin HPS_DDR3_ADDR[13] has GND driving its datain port Info (169070): Pin HPS_DDR3_ADDR[14] has GND driving its datain port Info (169070): Pin HPS_DDR3_DM[1] has GND driving its datain port Info (169070): Pin HPS_DDR3_DM[2] has GND driving its datain port Info (169070): Pin HPS_DDR3_DM[3] has GND driving its datain port Info (169070): Pin HPS_ENET_GTX_CLK has GND driving its datain port Info (169070): Pin HPS_ENET_MDC has GND driving its datain port Info (169070): Pin HPS_ENET_TX_DATA[0] has GND driving its datain port Info (169070): Pin HPS_ENET_TX_DATA[1] has GND driving its datain port Info (169070): Pin HPS_ENET_TX_DATA[2] has GND driving its datain port Info (169070): Pin HPS_ENET_TX_DATA[3] has GND driving its datain port Info (169070): Pin HPS_ENET_TX_EN has GND driving its datain port Info (169070): Pin HPS_SD_CLK has GND driving its datain port Info (169070): Pin HPS_SPIM_CLK has GND driving its datain port Info (169070): Pin HPS_SPIM_MOSI has GND driving its datain port Info (169070): Pin HPS_UART_TX has GND driving its datain port Info (169070): Pin HPS_USB_STP has GND driving its datain port Info (169070): Pin HPS_CONV_USB_N has VCC driving its datain port Info (169070): Pin HPS_ENET_INT_N has VCC driving its datain port Info (169070): Pin HPS_ENET_MDIO has VCC driving its datain port Info (169070): Pin HPS_GSENSOR_INT has VCC driving its datain port Info (169070): Pin HPS_I2C0_SCLK has VCC driving its datain port Info (169070): Pin HPS_I2C0_SDAT has VCC driving its datain port Info (169070): Pin HPS_I2C1_SCLK has VCC driving its datain port Info (169070): Pin HPS_I2C1_SDAT has VCC driving its datain port Info (169070): Pin HPS_KEY has VCC driving its datain port Info (169070): Pin HPS_LED has VCC driving its datain port Info (169070): Pin HPS_LTC_GPIO has VCC driving its datain port Info (169070): Pin HPS_SD_CMD has VCC driving its datain port Info (169070): Pin HPS_SD_DATA[0] has VCC driving its datain port Info (169070): Pin HPS_SD_DATA[1] has VCC driving its datain port Info (169070): Pin HPS_SD_DATA[2] has VCC driving its datain port Info (169070): Pin HPS_SD_DATA[3] has VCC driving its datain port Info (169070): Pin HPS_SPIM_SS has VCC driving its datain port Info (169070): Pin HPS_USB_DATA[0] has VCC driving its datain port Info (169070): Pin HPS_USB_DATA[1] has VCC driving its datain port Info (169070): Pin HPS_USB_DATA[2] has VCC driving its datain port Info (169070): Pin HPS_USB_DATA[3] has VCC driving its datain port Info (169070): Pin HPS_USB_DATA[4] has VCC driving its datain port Info (169070): Pin HPS_USB_DATA[5] has VCC driving its datain port Info (169070): Pin HPS_USB_DATA[6] has VCC driving its datain port Info (169070): Pin HPS_USB_DATA[7] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQ[8] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQ[9] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQ[10] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQ[11] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQ[12] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQ[13] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQ[14] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQ[15] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQ[16] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQ[17] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQ[18] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQ[19] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQ[20] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQ[21] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQ[22] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQ[23] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQ[24] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQ[25] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQ[26] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQ[27] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQ[28] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQ[29] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQ[30] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQ[31] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQS_N[1] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQS_N[2] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQS_N[3] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQS_P[1] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQS_P[2] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQS_P[3] has VCC driving its datain port Info (169186): Following groups of pins have the same dynamic on-chip termination control Info (169185): Following pins have the same dynamic on-chip termination control: msdma_fpga:u0|msdma_fpga_hps_0:hps_0|msdma_fpga_hps_0_hps_io:hps_io|msdma_fpga_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin HPS_DDR3_DQ[0] uses the SSTL-15 Class I I/O standard Info (169185): Following pins have the same dynamic on-chip termination control: msdma_fpga:u0|msdma_fpga_hps_0:hps_0|msdma_fpga_hps_0_hps_io:hps_io|msdma_fpga_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin HPS_DDR3_DQ[1] uses the SSTL-15 Class I I/O standard Info (169185): Following pins have the same dynamic on-chip termination control: msdma_fpga:u0|msdma_fpga_hps_0:hps_0|msdma_fpga_hps_0_hps_io:hps_io|msdma_fpga_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin HPS_DDR3_DQ[2] uses the SSTL-15 Class I I/O standard Info (169185): Following pins have the same dynamic on-chip termination control: msdma_fpga:u0|msdma_fpga_hps_0:hps_0|msdma_fpga_hps_0_hps_io:hps_io|msdma_fpga_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin HPS_DDR3_DQ[3] uses the SSTL-15 Class I I/O standard Info (169185): Following pins have the same dynamic on-chip termination control: msdma_fpga:u0|msdma_fpga_hps_0:hps_0|msdma_fpga_hps_0_hps_io:hps_io|msdma_fpga_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin HPS_DDR3_DQ[4] uses the SSTL-15 Class I I/O standard Info (169185): Following pins have the same dynamic on-chip termination control: msdma_fpga:u0|msdma_fpga_hps_0:hps_0|msdma_fpga_hps_0_hps_io:hps_io|msdma_fpga_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin HPS_DDR3_DQ[5] uses the SSTL-15 Class I I/O standard Info (169185): Following pins have the same dynamic on-chip termination control: msdma_fpga:u0|msdma_fpga_hps_0:hps_0|msdma_fpga_hps_0_hps_io:hps_io|msdma_fpga_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin HPS_DDR3_DQ[6] uses the SSTL-15 Class I I/O standard Info (169185): Following pins have the same dynamic on-chip termination control: msdma_fpga:u0|msdma_fpga_hps_0:hps_0|msdma_fpga_hps_0_hps_io:hps_io|msdma_fpga_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin HPS_DDR3_DQ[7] uses the SSTL-15 Class I I/O standard Info (169185): Following pins have the same dynamic on-chip termination control: msdma_fpga:u0|msdma_fpga_hps_0:hps_0|msdma_fpga_hps_0_hps_io:hps_io|msdma_fpga_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|diff_dtc_bar Info (169066): Type bi-directional pin HPS_DDR3_DQS_N[0] uses the Differential 1.5-V SSTL Class I I/O standard Info (169185): Following pins have the same dynamic on-chip termination control: msdma_fpga:u0|msdma_fpga_hps_0:hps_0|msdma_fpga_hps_0_hps_io:hps_io|msdma_fpga_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|diff_dtc Info (169066): Type bi-directional pin HPS_DDR3_DQS_P[0] uses the Differential 1.5-V SSTL Class I I/O standard Error (11802): Can't fit design in device. Modify your design to reduce resources, or choose a larger device. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. Error: Quartus Prime I/O Assignment Analysis was unsuccessful. 7 errors, 26 warnings Error: Peak virtual memory: 5552 megabytes Error: Processing ended: Sat Apr 27 03:20:34 2024 Error: Elapsed time: 00:00:45 Error: Total CPU time (on all processors): 00:00:37
What can I do to solve this problem?
Hi,
The error due to the width mismatch between the ports of top module DE10_NANO_SoC_GHRD.v and the ports of msdma_fpga.
Modify the lines below in DE10_NANO_SoC_GHRD.v then there'll be no error anymore after running the tcl script and I/O assignment analysis:
Line 29: output [/*14*/12: 0] HPS_DDR3_ADDR,
Line 37: inout [/*31*/7: 0] HPS_DDR3_DQ,
Line 39: inout /*[ 3: 0]*/ HPS_DDR3_DQS_P,
Thanks,
Regards,
Sheng
